FIFO with 2 clocks in VHDL -

i have problem vhdl assignment. need create fifo buffer between bus of 500mhz , bus of 30mhz.

i have designed basic fifo buffer

inputs: data_in, write_en, clk_500, read_en, clk_30, flushfifo.

outputs: data_out, full, empty.

this buffer designed using 2d array:

type fifo_arr array (0 63) of std_logic_vector(39 downto 0); signal fifo : fifo_arr := (others => (others => '0')); 

the problem following: how should write processes , maintain pointer between them synchronization? method have tried, code not synthesize (error:xst:827 signal ptr cannot synthesized)

any ideas?

thanks , regards

it might idea show code complained about!

fifos across clock domains tricky, not attempted lightly...

having said - looks homework assignment, read can found here:

http://eda.ee.nctu.edu.tw/jdhuang/courses/ipcd04/paper/alfke_final.pdf

(one of authors late, great, peter alfke - designed first fifo chip, in 1969, , regarded a, or the, fifo-guru)